• 04/03/2020
  • Public Content

In-place Processing with Advanced Tiling Kernels

Two dedicated kernel attributes (
) together control how intermediate buffers are used.
Usually, the OpenVX* runtime maintains separate intermediate buffers for the input and output of a node. For some kernels, it is possible to save memory and improve performance by using the same buffer. This is called an “in-place” buffer.
    is set to a function pointer of type
    typedef vx_int32 (*vx_inplace_params_intel_f) (vx_reference parameters[], vx_uint32 output_image_index);
    The intent of this function is to notify the runtime which input
    can be shared with a given output vx_image. The index of the given output
    parameter is passed in. This function should return the parameter index of the input
    which can share a buffer (be in-placed) with the given output
    . If the given output
    cannot be shared with any input
    , the function should return
    is set to a function pointer of type
    . This is the same function type as the advanced kernel function itself (that is passed in
    upon kernel registration). In many cases, the same kernel function can be used regardless of whether "in-place" buffers are used of not.
Even if both of these attributes are set, the OpenVX* runtime can ignore the request for "in-place" buffers in certain situations. For example, if the input
is not a virtual image, or if the input buffer is shared with another node.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804