User and Reference Guide

  • 2020
  • 07/29/2020
  • Public Content
Contents

Architectural Registers

Architectural target registers (CPU registers) are displayed in the Registers view.
To monitor the value of an architectural register:
  1. Halt the target by pressing the
    suspend
    Suspend button.
  2. Open the Registers view and navigate to the desired register by expanding the register tree.
  3. Right click the table row with register information and select Watch In Expressions.
    The Expression view opens displaying the selected register value.
To modify an architectural register:
  1. Halt the target by pressing the
    suspend
    Suspend button.
  2. In the Registers view, navigate to the register you want to modify by expanding the register tree.
  3. Under the Hex or Decimal column click the value you want to change and enter the new one.
  4. The register tree is refreshed and the changed register is highlighted yellow.
Alternatively, you can use the Value column in the Expression view to modify the register value.
Viewing Registers for Different Hardware threads
To display registers associated with different hardware threads simultaneously, configure the Intel® System Debugger GUI the following way:
  1. Halt the target by pressing the
    suspend
    Suspend button.
  2. Open the Registers view.
  3. By clicking the
    open new view
    Open New View button, create as many Registers views as needed.
  4. For each Registers view:
    • In the Debug view, select a hardware thread.
    • In the Registers view, click
      pin view
      Pin to Debug Context to pin the view to the chosen hardware thread.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804