User and Reference Guide

  • 2020
  • 10/23/2020
  • Public Content

Reliable Target Connection

With a reliable target connection, the signaling requirements of JTAG are met, and communication at the JTAG protocol level is possible. Additionally, there may be sideband signals that are not part of the generic JTAG spec but are required for debugging Intel® processors. Specific requirements for each platform are described in the "Debug Port Design Guide" available from Intel.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804