User and Reference Guide

  • 2020
  • 07/29/2020
  • Public Content
Contents

Watchdog Timers

Watchdog Timers can be implemented in the platform, the firmware/OS, or some combination of the two.
  • Platform Watchdog Timers are implemented by a non-CPU device that can reset the platform if a heartbeat condition is not seen. If the heartbeat is implemented in software then halting the target via JTAG can result in spontaneous resets, either while the target is halted, or immediately after resuming execution.
  • Firmware/OS Watchdog Timers are implemented entirely in software but may rely on hardware resources such as the Time Stamp Counter to detect hangs on a CPU. If the debugger does not control the simultaneous run/stop of all threads properly then the OS may detect this as an error condition.

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804