User and Reference Guide

  • 2020
  • 10/23/2020
  • Public Content
Contents

Instruction Trace View

Displays the history of instructions executed since tracing is enabled.
Menu
Window > Show View > Other > Intel® System Debugger > Instruction Trace View
Toolbar
registers view
Instruction Trace View
The Instruction Trace View shows the chronological order of instruction calls captured by the Last Branch Record (LBR).
The view contains five columns:
  • Address: the assembler instruction address.
    Instructions are grouped by the line number. Expandable Address items display multiple instructions called from a single code line.
  • Instruction
    : the instruction syntax.
    Note
    If the thread selected in the
    Debug
    view contains no symbols loaded, the following columns are empty.
  • Module
    : the name of the running module.
  • File Name
    : the name of the source code file.
  • Line Number
    : the number of the source file line that calls the instruction.
    To view the line in the source file, double-click the line number. The source file opens in a new view and the selected line is highlighted.
  • File Path
    : path to the source file.
View Toolbar Options
resume
Start Instruction Trace
Starts or resumes the terminated instruction trace.
terminate
Stop Instruction Trace
Stops the running instruction trace.
show target breakpoints
Configure Instruction Trace
Opens a dialog box that allows you to configure the trace type. Currently, only Last Branch Record (LBR) is supported.
refresh view
Refresh View
Refreshes the view and updates the instruction history.
pin view
Pin to Hardware Thread
Pins the view to an active hardware thread displayed in the Debug view. If pinned, the view shows the instruction trace history only for the chosen thread (the name is displayed above the table) and is not refreshed if another thread is selected.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804