• 2020
  • 03/31/2020
  • Intel Confidential
Contents

Overview


In addition to loop parallelism, the Intel® Threading Building Blocks (Intel® TBB) library also supports graph parallelism. It's possible to create graphs that are highly scalable, but it is also possible to create graphs that are completely sequential.
There are 3 types of components used to implement a graph:
  • A
    graph
    object
  • Nodes
  • Edges
Nodes invoke user-provided function objects or manage messages flow to/from other nodes. There are pre-defined nodes that buffer, filter, broadcast or order items as they flow through the graph.
Edges are the connections between the nodes, managed by calls to the
make_edge
and
remove_edge
functions.
The
graph
object is the owner of the tasks created on behalf of the flow graph. Users can wait on the
graph
if they need to wait for the completion of all of the tasks related to the flow graph execution. One can also register external interactions with the
graph
and run tasks under the ownership of the flow graph.
Note
The tasks related to the flow graph are executed in the
task_group_context
of that flow graph. If no context is specified when a flow graph is created, a new context is created and bound to the enclosing context.
The context a body of a flow graph node is executed in is that node's graph. If a cancellation or exception occurs in that node, the context of its graph is cancelled, and if necessary the exception thrown is passed to the enclosing context for further processing.
Parent topic: Flow Graph

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804