Developer Guide

  • 2021.2
  • 06/11/2021
  • Public
Contents

Run the Sample

In this sample,
phc2sys
synchronizes the PTP hardware clock (PHC) with CLOCK_REALTIME. The presence of hardware-assisted cross-timestamping increases clock synchronization precision. This sample demonstrates how to evaluate the level of precision. The sample generates two simultaneous periodic signals. One signal is generated by the pulse per signal (PPS) pin of the network controller and the second is generated by the TGPIO pin.
The Always Running Timer (ART) is used as a clock source for CLOCK_REALTIME and TGPIO. Two periodic signals are generated, one by the PPS pin and one by the TGPIO pin. Both signals have the same period and the same start timestamp.
phc2sys
runs clock adjustment in a loop. It reads both CLOCK_REALTIME and PHC simultaneously using hardware-assisted cross-timestamping (if present) to calculate an offset and a clock ratio. It adjusts PHC to synchronize the corresponding edges of the two signals. A logic analyzer is used to capture both signals and analyze them to see how precisely the clocks are synchronized.
ptp4l
is required for the specific Ethernet card that supports signal generation and signal reading at the same time, which is required for the sample.
In this sample, TGPIO is also synchronized with CLOCK_REALTIME to compensate for possible drift, because CLOCK_REALTIME is not exactly the same as ART.
To run the example:
  1. Connect TGPIO pin 1 to channel 0 of the logic analyzer. Connect PPS pin to channel 1 of the logic analyzer. Connect the ground pin to the ground of the logic analyzer (any channel).
    For 11th Gen Intel® Core™ Processors, use the PPS pin of the add-in card (AIC).
    For Intel Atom® x6000E Series Processors, use the PSE GBE1.
    The names “TGPIO pin 1” and “PPS pin” are placeholders. For information about pins specific to your hardware, see Example Pins.
    For Intel Atom® x6000E Series Processors, configure PSE GBE1 before running the sample:
    1. Open the BIOS.
    2. Go to
      Intel Advanced Menu
      >
      PCH-IO Configuration
      >
      PSE Configuration
      .
    3. Set
      GBE1
      to
      Host owned with pin muxed
      .
    4. Save your changes and exit the BIOS. The system reboots.
  2. Run the synchronization script:
    tcc_ethernet_sample_start_synchronization
    Ouput example:
    Ethernet interface name: eth2 Starting ptp4l... ptp4l[1370.895] selected /dev/ptp3 as PTP clock ptp4l[1370.906] port 1: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[1370.907] port 0: INITIALIZING to LISTENING on INIT_COMPLETE ptp4l[1370.907] port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES ptp4l[1370.907] selected local clock 88abcd.fffe.110123 as best master ptp4l[1370.907] port 1: assuming the grand master role PTP device: /dev/ptp3 Starting ph2sys... Use Ctrl+C to exit. phc2sys[1376.912]: /dev/ptp3 sys offset 1094843 s0 freq -293962 delay 0 phc2sys[1377.913]: /dev/ptp3 sys offset 1095927 s1 freq -292879 delay 0 phc2sys[1378.914]: /dev/ptp3 sys offset -30 s2 freq -292909 delay 0 phc2sys[1379.914]: /dev/ptp3 sys offset -24 s2 freq -292912 delay 0 phc2sys[1380.914]: /dev/ptp3 sys offset -19 s2 freq -292914 delay 0 phc2sys[1381.925]: /dev/ptp3 sys offset -2 s2 freq -292902 delay 0
  3. Monitor the values in the phc2sys output. When the values stop decreasing, synchronization is complete.
  4. In the second terminal window, run the sample to start signal generation. Use the “PTP device” from the synchronization script output as the PPS device (
    /dev/ptp3
    in the following example):
    tcc_ethernet_timestamps_sample --tgpio /dev/ptp0 1 --pps /dev/ptp3 0 --period 1000000000
    Output example:
    Started PPS signal generation. Pin/channel 0, period 1000000000 nsec To interrupt, use Ctrl+C Generated single pulse on TGPIO. Start time: 196177158691ns Generated single pulse on TGPIO. Start time: 196677158643ns Generated single pulse on TGPIO. Start time: 197177158629ns Generated single pulse on TGPIO. Start time: 197677158615ns Generated single pulse on TGPIO. Start time: 198177158601ns
    The sample uses the hardware Cross-Timestamping feature to read clocks simultaneously.
  5. Use a logic analyzer to read the values of the two signals. Both signals are generated with the same start timestamp in the CLOCK_REALTIME time domain. If PHC is synchronized with CLOCK_REALTIME, the edges of the signals will align.
  6. Export the measurement results as a CSV file:
    Example (results.csv):
    0.000000000000000, 0, 1 0.012241160000000, 0, 0 0.014060560000000, 1, 0 0.062242840000000, 1, 1 0.064062200000000, 0, 1 0.112244520000000, 0, 0 0.114063880000000, 1, 0 0.162246200000000, 1, 1 0.164065560000000, 0, 1 0.212247880000000, 0, 0
  7. Run the signal analyzer script to plot the results.
    cd samples/plot_scripts ./tcc_signal_analyzer_plotter.py results.csv --shift --units ns --output plot.png
    Output example (plot.png):

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.