Developer Guide

  • 2021.2
  • 06/11/2021
  • Public
Contents

Run the Sample

To run this example:
  1. Connect the TGPIO pin 0 to channel 0 of the logic analyzer. Connect the ground pin to the ground pin of the logic analyzer (any channel).
    The name “TGPIO pin 0” is a placeholder. For information about pins specific to your hardware, see Example Pins.
  2. Generate a baseline periodic signal without frequency discipline. The period of the signal is a multiple of the TGPIO clock period and can be generated exactly. This signal will be used as a baseline.
    1. Run the sample with zero PI-controller gains, which means no control:
      tcc_tgpio_frequency_discipline_sample --pin 0 -T 76875 -p 0 -i 0
      Output example:
      Start generating signal. To interrupt, use Ctrl+C Period adjustment: 0.000000 ns Period : 76.875000 us Period adjustment: 0.000000 ns Period : 76.875000 us
      The sample prints the current controlled period and period adjustment on the PI controller iteration.
      Period
      is the next period value that will be passed to the TGPIO.
      Period adjustment
      is how the period is changed based on PI controller calculations. In this example, gains of the PI controller are zero, so no adjustment occurred.
    2. In the logic analyzer software, start data capture on channel 0 for several seconds.
    3. Stop the sample (Ctrl+C).
    4. Export the data from the logic analyzer software as
      baseline.csv
      .
  3. Generate a periodic signal without frequency discipline. The period of the signal is not a multiple of the TGPIO clock period, and the actual signal period will be different.
    1. Run the sample with zero PI-controller gains, which means no control:
      tcc_tgpio_frequency_discipline_sample --pin 0 -T 76896 -p 0 -i 0
      Output example:
      To interrupt, use Ctrl+C Period adjustment: 0.000000 ns Period : 76.896000 us Period adjustment: -0.000000 ns Period : 76.896000 us
    2. In the logic analyzer software, start data capture on channel 0 for several seconds.
    3. Stop the sample (Ctrl+C).
    4. Export the data from the logic analyzer software as
      no_discipline.csv
      .
  4. Generate a signal with frequency discipline:
    1. Run the sample with PI-controller gains, which will get good results:
      tcc_tgpio_frequency_discipline_sample --pin 0 -T 76896 -p 0.01 -i 0.001
      Output example:
      Start generating signal. To interrupt, use Ctrl+C Period adjustment: 256.088989 ns Period : 77.152089 us Period adjustment: -6.572001 ns Period : 77.145517 us Period adjustment: -9.686001 ns Period : 77.135831 us
      In this example, period adjustment is not zero, because the PI controller adjusts the signal period.
    2. In the logic analyzer software, start data capture on channel 0 for several seconds
    3. Stop the sample (Ctrl+C).
    4. Export the data from the logic analyzer software as
      discipline.csv
      .
  5. Analyze the captured data with the provided script:
    1. Go to the script directory:
      cd ${TCC_ROOT}/samples/plot_scripts
    2. Copy the CSV files from the previous steps to this directory.
    3. Run the script to analyze results:
      ./tcc_tgpio_frequency_discipline_sample_plotter.py no_discipline.csv,76896 discipline.csv,76896 baseline.csv,76875
Output Example
For example purposes, the following graph shows the results of the frequency discipline from an 11th Gen Intel® Core™ processor system.
This graph shows accumulated phase error (in LaTex Math image.) over time. See About the Sample for details about phase error calculation.
The green line is the baseline, which has the smallest possible phase error. The baseline does not have a zero phase error, because the ART clock and the logic analyzer clock are not synchronized. The Saleae* Logic Pro 16 logic analyzer was used to create this example graph, and it has +/- .005% time error that is consistent with observed results.
The blue line is the phase error of the frequency that cannot be generated exactly without using frequency discipline. This signal has a significant and rapidly growing phase error.
The orange line is the phase error of the same frequency, but generated with frequency discipline. The average phase error is very close to the baseline, which means that there is no growing phase error.

Product and Performance Information

1

Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.