User Guide

Contents

Hardware Event List

If required, edit a list of PMU events monitored by the
Intel® VTune™
Profiler
for your processor by modifying an existing or creating a new hardware event-based sampling (EBS) analysis configuration.
To add events:
  1. In the
    HOW
    pane, select an existing hardware event-based analysis (for example, Microarchitecture Exploration) and click the
    Copy
    button to create a custom copy of this configuration.
    The new analysis type shows up under the
    Custom Analysis
    group in the
    HOW
    pane.
  2. From the list of PMU events supported for the current platform, select the events you want the
    VTune
    Profiler
    to monitor in your new configuration.
    You may select an event and click the
    Explain...
    button at the bottom to open the and read more details on the selected event.
    To filter in/out the event list for particular event(s), specify search keywords (applied to both the
    Event Name
    and
    Event Description
    columns) in the
    Filter
    field.
    Usually precise events have a _PS postfix (for example, UOPS_RETIRED.RETIRE_SLOTS_PS) and/or a clear indication (Precise Event) in the Event Description column.
  3. Click
    Start
    to run your new analysis configuration.
You may configure the
VTune
Profiler
to monitor all the events in a single collection run using event multiplexing or allow multiple runs to collect more precise event data.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804