User Guide

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Hardware Event Skid

Event skid is the recording of an event not exactly on the code line that caused the event.
Event skids may even result in a caller function event being recorded in the callee function.
Event skid is caused by a number of factors:
  • The delay in propagating the event out of the processor's microcode through the interrupt controller (APIC) and back into the processor.
  • The current instruction retirement cycle must be completed.
  • When the interrupt is received, the processor must serialize its instruction stream which causes a flushing of the execution pipeline.
Intel® processors support accurate event location for some events. These events are called precise events.
The event skid affects the accuracy of your analysis results. When the grouping level is very small (for example, instruction, source line, or basic block), the
Intel® VTune™
Profiler
attributes performance results incorrectly. For example, when row A induces a problem, row B shows up as a hotspot. If different CPU events in the formula of a hardware event-based metric have different skids, the
VTune
Profiler
may attribute data to different blocks, which makes all metrics invalid. This type of issue typically does not show up at the function granularity.
Example: Interpreting Jump and Call Instructions
Events that happen in the execution time of the
jmp
or
call
instruction, may appear on an instruction that is one or two instructions away from original
jmp
/
call
in the execution flow. In this example, the
mov
instruction at the top of the loop is not responsible for the 1.02% of the events because the
mov
instruction is the target of the branch at the bottom of the loop. The real source of the events is the
jmp
instruction at the bottom of the loop.
Event %
Instructions
1.02%


    
top_of_loop: mov ... ... (any number of lines) end_of_loop: jnz <to someplace> jmp top_of_loop

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804