User Guide

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Instructions Retired Event

The Instructions Retired is an important hardware performance event that shows how many instructions were completely executed.
Modern processors execute much more instructions that the program flow needs. This is called a
speculative execution
. Instructions that were "proven" as indeed needed by the program execution flow are "retired".
In the Core Out Of Order pipeline leaving the Retirement Unit means that the instructions are finally executed and their results are correct and visible in the architectural state as if they execute in-order:
Retirement and write back of state to visible registers is only done for instructions and uops that are on the correct execution path. Instructions and uops of incorrectly predicted paths are flushed upon identification of the misprediction and the correct paths are then processed. Retirement of the correct execution path instructions can proceed when two conditions are satisfied:
  • The uops associated with the instruction to be retired have completed, allowing the retirement of the entire instruction, or in the case of instructions that generate very large number of uops, enough to fill the retirement window.
  • Older instructions and their uops of correctly predicted paths have retired.
Intel® VTune™
Profiler
monitors the Instructions Retired event for all analysis types based on the hardware event-based sampling (EBS), also known as Performance Monitoring Counter (PMC) analysis in the sampling mode. The Instructions Retired event is also part of the basic Clockticks per Instructions Retired (CPI) metric that shows how much latency affected an application execution.
For performance analysis, you may check how many instructions started their execution in OOO pipeline (
ISSUED
counter or
EXECUTED
counter) and compare the number with the count of retired operations. High difference shows that CPU does a lot of useless work and uses excess power.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804