User Guide

  • 2020
  • 06/18/2020
  • Public Content

Precise Events

Precise events are events for which the exact instruction addresses that caused the event are available.
You can configure these events to collect extended information, the values of all the registers evaluated at the IP of the interrupt, on IA-32 and Intel® 64 architecture systems. For example, on Intel Core™ 2 processor family, an L2 load miss that retrieves a cacheline can be identified with the MEM_LOAD_RETIRED.L2_LINE_MISS event. The register values and the disassembly allows the reconstruction of the linear address of the memory operation that caused the event.
Check the
configuration pane in the
Configure Analysis
window to make sure the events you use are precise. Usually precise events have a _PS postfix (for example, MEM_LOAD_RETIRED.FB_HIT_PS) in the
column as follows:

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804