User Guide

  • 2020
  • 06/18/2020
  • Public Content

CPU/FPGA Interaction View

This is a
. A preview feature may or may not appear in a future production release. It is available for your use in the hopes that you will provide feedback on its usefulness and help determine its future. Data collected with a preview feature is not guaranteed to be backward compatible with future releases. Please send your feedback to or to
Use the CPU/FPGA Interaction viewpoint to assess FPGA performance of executed kernels, overall time for memory transfers between the CPU and FPGA, and how well a workload is balanced between the CPU and FPGA.
To interpret the performance data provided in the CPU/FPGA Interaction viewpoint, you may follow the steps below:

Define a Performance Baseline

Start with exploring the
window that provides general information on your application execution. Key areas for optimization include application execution time, tasks with high CPU or FPGA time, and kernel execution time.
Use the Elapsed Time value as a baseline for comparison of versions before and after optimization.

Assess FPGA Utilization

Look at the
FPGA Top Compute Tasks
list on the
window for a list of kernels running on the FPGA. Switch to the
window and use the
Computing Task Purpose / Source Computing Task (FPGA)
grouping to view the hotspots for kernels.
You can click a task from the
FPGA Top Compute Tasks
list to be taken to that task on the
Review the
FPGA Utilization
timeline, which shows how many kernels and transfers are executing at the same time on the FPGA.

Review Memory Transfers

Look at the
Data Transferred
column on the
window or the
Computing Queue
rows on the
window to view the FPGA kernels and memory transfers.

Review FPGA Device Metrics

Global Bandwidth
metrics to see how efficiently your kernels run on the FPGA device.

Determine Workload Impact

Context Switch Time
metric on the
window shows the amount of time the CPU spent in context switches. Switch to the
window and hover over the timeline to view the reason for the context switch. In some cases, CPU context switches may represent CPU waits for the FPGA. Look at the FPGA Utilization line to identify times when the CPU may have been waiting on the FPGA and vice versa. For instance, when there is no FPGA activity, but CPU activity is high, it is likely that the FPGA is waiting for the CPU to complete a preparation step.

Analyze Source of the Host Application Part

Double-click the function you want to optimize to view its related source code file in the Source/Assembly window. You can open the code editor directly from the
Intel® VTune™
and edit your code (for example, minimizing the number of calls to the hotspot function).

Analyze Source of the Kernel Running on an FPGA Device

Double-click the kernel to see FPGA device metrics per the kernel source lines. Use the Source view to see what channels and memories cause most stalls and how much data they transfer.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804