User Guide


Command Line Analysis

Use the CPU/FPGA Interaction analysis to assess the balance between CPU and FPGA in systems with FPGA hardware that run Data Parallel C++ (DPC++) or OpenCL™ applications. Review FPGA time spent executing kernels, overall time for memory transfers between the CPU and FPGA, and wait time impact on CPU and FPGA work loads.
This is a
. A preview feature may or may not appear in a future production release. It is available for your use in the hopes that you will provide feedback on its usefulness and help determine its future. Data collected with a preview feature is not guaranteed to be backward compatible with future releases. Please send your feedback to or to


-collect fpga-interaction [-knob <
>] [--] <
For the most current information on available knobs (configuration options) for the CPU/FPGA Interaction analysis, enter:
-help collect fpga-interaction
This example runs the CPU/FPGA Interaction analysis on an application with stack collection enabled:

vtune -collect fpga-interaction -knob enable-stack-collection=true -- /home/test/myApplication

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804