User Guide

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Front-End Bandwidth DSB

Metric Description

This metric represents a fraction of cycles during which CPU was likely limited due to DSB (decoded uop cache) fetch pipeline. For example, inefficient utilization of the DSB cache structure or bank conflict when reading from it, are categorized here.

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.