Lock Latency
Metric Description
This metric represents cycles fraction the CPU
spent handling cache misses due to lock operations. Due to the
microarchitecture handling of locks, they are classified as L1 Bound regardless
of what memory source satisfied them.
Possible Issues
A significant fraction of CPU cycles spent handling cache misses due
to lock operations. Due to the microarchitecture handling of locks, they are
classified as L1 Bound regardless of what memory source satisfied them. Note
that this metric value may be highlighted due to Store Latency issue.