L1I Stall Cycles
Metric Description
In a shared-memory machine, instructions and data
are stored in the same memory address space. However, for performance, they are
cached separately. Large code working set, branch misprediction, including one
caused by excessive use of virtual functions, can induce misses into L1I and so
cause instruction starvation that badly influence application performance.
Possible Issues
A significant number of CPU cycles is spent waiting for code to arrive
into L1I. Review application code for the patterns causing instruction
starvation and rearrange the code.