Certain events require the entire pipeline to be
cleared and restarted from just after the last retired instruction. This metric
measures only self-modifying code (SMC) events. This event counts the number of
times a program writes to a code section that is shared with another processor
or itself as a data page, causing the entire pipeline and the trace caches to
be cleared. Self-modifying code causes a severe penalty in all processors based
on Intel architecture.
A significant portion of execution time is spent handling machine
clears incurred by self-modifying code event. Dynamically-modified code (for
example, target fix-ups) is likely to suffer from performance degradation due
to SMC. To avoid this, introduce indirect branches and use data tables on data
pages (not code pages) with register-indirect calls.