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Typed Writes Coalescence

Metric Description

Transaction Coalescence is a ratio of the used bytes to all bytes requested by the transaction. The lower the coalescence, the bigger part of the bandwidth is wasted. It originates from the GPU Data Port function that dynamically merges scattered memory operations into fewer operations over non-duplicated 64-byte cacheline requests. For example, if a 16-wide SIMD operation consecutively reads integer array elements with a stride of 2, the coalescence of such a transaction is 50%, because half of the bytes in the requested cacheline is not used.

Product and Performance Information

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Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex.