5-Level Paging and 5-Level EPT White Paper

Submitted: May 24, 2018 Last updated: May 24, 2018
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Detailed Description

This document describes planned extensions to the Intel® 64 architecture to expand the size of addresses that can be translated through a processor’s memory-translation hardware.

NOTE: Intel® Memory Protection Extensions (Intel® MPX) have been deprecated and are not available on all future processors.


Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804