Parallel Universe Magazine - Issue 18, June 2014

Submitted: June 01, 2014 Last updated: June 01, 2014
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Detailed Description

Contents:

  • Letter from the Editor, by James Reinders
    Speaking in Code
     
  • Graduate from MIT to GCC Mainline with Intel® Cilk™ Plus
    Intel® Cilk™ Plus provides a higher level of abstraction than other threading frameworks. This article explores its capabilities for expressing task and data parallelism.
     
  • Flow Graphs, Speculative Locks, and Task Arenas in Intel® Threading Building Blocks
    A look at Intel® TBB features, including the flow graph interface, speculative locks that take advantage of the Intel® Transactional Synchronization Extensions (Intel® TSX) technology, and user-managed task arenas that provide enhanced concurrency control and work isolation.
     
  • 20 Years of the MPI Standard: Now with a Common Application Binary Interface
    Examines MPI compatibility issues and resolution, as well as the potential of the upcoming common MPI Application Binary Interface (ABI).
     
  • Mastering Performance Challenges with the New MPI-3 Standard
    Find out how to measure the overlap of communication and computation, and how an MPI application can benefit from nonblocking collective communication.
     
  • An OpenMP* Timeline
    An infographic time-capsule of OpenMP*.
     
  • Leverage Your OpenCL™ Investment on Intel® Architectures
    Get more out of OpenCL™—from cross-device portability to the Intel® Xeon Phi™ coprocessor.
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Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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