Parallel Universe Magazine - Issue 25, June 2016

Submitted: July 01, 2016 Last updated: July 01, 2016
  • File:
    intel-parallel-universe-issue-25.pdf
  • Size:
    18.76 MB
Download

Detailed Description

Contents:

  • Letter from the Editor: Democratization of HPC, by James Reiders
    James Reinders, an expert on parallel programming, is coauthor of the new Intel® Xeon Phi™ Processor High Performance Programming—Knights Landing Edition.
     
  • Supercharging Python* with Intel and Anaconda* for Open Data Science, by Travis Oliphant
    The technologies that promise to tackle Big Data challenges.
     
  • Getting Your Python* Code to Run Faster Using Intel® VTune™ Amplifier XE, by Kevin O’Leary
    Providing line-level profiling information with very low overhead.
     
  • Parallel Programming with Intel® MPI Library in Python*, by Artem Ryabov and Alexey Malhanov
    Guidelines and tools for improving performance.
     
  • The Other Side of the Chip, by Robert Ioffe
    Using Intel® Processor Graphics for Compute with OpenCL™.
     
  • A Runtime-Generated Fast Fourier Transform for Intel® Processor Graphics, by Dan Petre, Adam T. Lake, and Allen Hux
    Optimizing FFT without increasing complexity.
     
  • Indirect Calls and Virtual Functions Calls: Vectorization with Intel® C/C++ 17.0 Compilers, by Hideki Saito, Serge Preis, Sergey Kozhukhov, Xinmin Tian, Clark Nelson, Jennifer Yu, Sergey Maslov, and Udit Patidar
    The newest Intel® C++ Compiler introduces support for indirectly calling a SIMD-enabled function in a vectorized fashion.
     
  • Optimizing an Illegal Image Filter System, by Yueqiang Lu, Ying Hu, and Huaqiang Wang
    Tencent doubles the speed of its illegal image filter system using a SIMD instruction set and Intel® Integrated Performance Primitives.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804