Parallel Universe Magazine - Issue 27, January 2017

Submitted: January 01, 2017 Last updated: January 01, 2017
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Detailed Description


  • Letter from the Editor: The Changing HPC Landscape Still Looks the Same, by Henry A. Gabb
    Henry A. Gabb is a long-time high-performance and parallel computing practitioner and has published numerous articles on parallel programming.
  • The Present and Future of the OpenMP* API Specification, by Michael Klemm, Alejandro Duran, Ravi Narayanaswamy, Xinmin Tian, and Terry Wilmarth
    How the gold standard parallel programming language has improved with each new version.
  • Reducing Packing Overhead in Matrix-Matrix Multiplication, by Kazushige Goto, Murat Efe Guney, and Sarah Knepper
    Improve performance on multicore and many-core Intel® architectures, particularly for deep neural networks.
  • Identify Scalability Problems in Parallel Applications, by Vladimir Tsymbal
    How to improve scalability for Intel® Xeon® and Intel® Xeon Phi™ Processors using new Intel® VTune™ Amplifier memory analysis.
  • Vectorization Opportunities for Improved Performance with Intel® AVX-512, by Martyn Corden
    Examples of how Intel® Compilers can vectorize and speed up loops.
  • Intel® Advisor Roofline Analysis, by Kevin O’Leary, Ilyas Gazizov, Alexandra Shinsel, Zakhar Matveev, and Dmitry Petunin
    A new way to visualize performance optimization trade-offs.
  • Intel-Powered Deep Learning Frameworks, by Pubudu Silva
    Your path to deeper insights.

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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