Parallel Universe Magazine - Issue 30, October 2017

Submitted: October 01, 2017 Last updated: October 01, 2017
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Detailed Description

Contents:

  • Letter from the Editor: Meet Intel® Parallel Studio XE 2018, by Henry A. Gabb
    Henry A. Gabb is a long-time high-performance and parallel computing practitioner and has published numerous articles on parallel programming.
     
  • Driving Code Performance with Intel® Advisor’s Flow Graph Analyzer, by Vasanth Tovinkere, Pablo Reble, Farshad Akhbari, and Palanivel Guruvareddiar
    Optimizing performance for an autonomous driving application.
     
  • Welcome to the Adult World, OpenMP*, by Barbara Chapman
    After 20 years, it’s more relevant than ever.
     
  • Enabling FPGAs for Software Developers, by Bernhard Friebe, and James Reinders
    Boosting efficiency and performance for automotive, networking, and cloud computing.
     
  • Modernize Your Code for Performance, Portability, and Scalability, by Jackson Marusarz
    What’s new in Intel® Parallel Studio XE.
     
  • Dealing with Outliers, by Oleg Kremnyov, Mikhail Averbukh, and Ivan Kuzmin
    How to find fraudulent transactions in a real-world dataset.
     
  • Tuning for Success with the Latest SIMD Extensions and Intel® Advanced Vector Extensions 512, by Xinmin Tian, Hideki Saito, Sergey Kozhukhov, and Nikolay Panchenko
    Best practices for taking advantage of the latest architectural features.
     
  • Effectively Using Your Whole Cluster, by Rama Kishan Malladi
    Optimizing SPECFEM3D_GLOBE* performance on Intel® architecture.
     
  • Is Your Cluster Healthy?, by Brock A. Taylor
    Must-have cluster diagnostics in Intel® Cluster Checker.
     
  • Optimizing HPC Clusters, by Michael Hebenstreit
    Enabling on-demand BIOS configuration changes in HPC clusters.
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Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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