Parallel Universe Magazine - Issue 36, April 2019

Submitted: April 09, 2019 Last updated: April 09, 2019
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Detailed Description

Contents:

  • Letter from the Editor: Onward to Exascale Henry A. Gabb, Senior Principal Engineer, Intel Corporation
     
  • Effectively Train and Execute Machine Learning and Deep Learning Projects on CPUs Nathan Greeneltch and Jing Xu, Software Technical Consulting Engineers, Intel Corporation
     
  • Parallelism in Python* Using Numba* David Liu, Software Technical Consulting Engineer, Intel Corporation
     
  • Boosting the Performance of Graph Analytics Workloads Stijn Eyerman, Wim Heirman, and Kristof Du Bois, Research Scientists, and Joshua B. Fryman and Ibrahim Hur, Principal Engineers, Intel Corporation
     
  • How Effective is Your Vectorization? Kevin O’Leary, Technical Consulting Engineer, Intel Corporation
     
  • Improving Performance using Vectorization for Particle-in-Cell Codes Bei Wang, HPC Software Engineer, Princeton University; Carlos Rosales-Fernandez, Software Technical Consulting Engineer, Intel Corporation; and William Tang, Professor, Princeton Plasma Physics Laboratory
     
  • Boost Performance for Hybrid Applications with Multiple Endpoints in Intel® MPI Library Rama Kishan Malladi, Graphics Performance Modeling Engineer, and Dr. Amarpal Singh Kapoor, Technical Consulting Engineer, Intel Corporation
     
  • Innovate System and IoT Apps Ramya Chandrasekaran and Thorsten Moeller, Product Marketing Engineers, Intel Corporation
     

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804