Parallel Universe Magazine - Issue 38, August 2019

Submitted: October 04, 2019 Last updated: October 04, 2019
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Detailed Description


  • Letter from the Editor: See You at the Intel® HPC Developer Conference by Henry A. Gabb, Senior Principal Engineer, Intel Corporation
  • Accelerating XGBoost* for Intel® Xeon® Processors: How to Maximize Processor Performance for Machine Learning by Egor Smirnov, Software Engineering Manager, Intel Corporation
  • Detecting and Mitigating False Sharing in Multi-Processors: Get Big Performance Benefits for Your Multithreaded Applications by Ramesh Peri, Senior Principal Engineer, Intel Corporation
  • Speeding Up Simulation Analysis with yt* and Intel® Distribution for Python*: How to Boost Speed up to 4.6x on Intel® Xeon® Scalable Processors by Salvatore Cielo, PhD, Scientific Computing Expert, Leibniz Supercomputing Centre; Luigi Iapichino, PhD, Scientific Computing Expert, Leibniz Supercomputing Centre; Fabio Baruffa, PhD, Technical Consulting Engineer, Intel Corporation
  • Intel® Software Guard Extensions: Using Hardware-Based Isolation and Memory Encryption to Provide More Code Protection in your Solutions by Rama Kishan Malladi, Performance Modeling Engineer, Intel Corporation
  • Verizon Maximizes Customer Satisfaction: Optimizing Application Performance with Powerful Profiling, Guest Editorial by Dennis O’Connell, Senior Director of Performance Engineering, Verizon
  • Composable Threading Is Coming to Julia*: Flexible Parallelism in a Productivity Language Editorial by Henry A Gabb, Senior Principal Engineer, Intel Corporation

Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804