Parallel Universe Magazine - Issue 41, July 2020

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Detailed Description

Contents:

 

  • Letter from the Editor: Hello from My Home Office by Henry A. Gabb, Senior Principal Engineer, Intel Corporation
  • DPC++ for Intel® Processor Graphics Architecture by Rama Malladi, Graphics Performance Modeling Engineer, Intel Corporation
  • Using OpenMP Offload for Programming Heterogeneous Architectures by Jose Noudohouenou, Software Engineer, and Nitya Hariharan, Application Engineer, Intel Corporation
  • Delving into the Mysteries of OpenMP SIMD Support by Clay P. Breshears, PhD, Principal Engineer, Omics Data Automation, Inc.
  • Making the Most of Intel® Compiler Optimization Reports by Mayank Tiwari, Technical Consulting Engineer, and Rama Malladi, Graphics Performance Modeling Engineer, Intel Corporation
  • Overlapping Computation and Communication in HPC Applications by Fabio Baruffa, PhD, Senior Software Applications Engineer, Intel Corporation
  • Making HPC Clusters More Efficient Using Intel® MPI Library by Dr. Amarpal Singh Kapoor, Technical Consulting Engineer, and Marat Shamshetdinov, Software Development Engineer, Intel Corporation
  • Taking Data Science Applications to the Next Level with OmniSci by Venkat Krishnamurthy, Vice President of Product Management, OmniSci
     

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804