Parallel Universe Magazine - Issue 42, October 2020

  • File:
    parallel-universe-issue-42.pdf
  • Size:
    15.00 MB
Download

Detailed Description

Contents:

  • Letter from the Editor: One Year into the oneAPI Era by Henry A. Gabb, Senior Principal Engineer, Intel 
  • Programming Data Parallel C++ by Jeff Hammond, Principal Engineer, Intel Data Center Group 
  • Building an Open, Standards-Based Ecosystem for Heterogeneous Parallelism by Andrew Richards, CEO and Founder, Codeplay
  • A Vendor-Neutral Path to Math Acceleration by Mehdi Goli, Principal Software Engineer, Codeplay Software, and Maria Kraynyuk, Software Engineer, Intel Corporation
  • How to Speed Up Performance by Exploring GPU Configurations by Kevin O’Leary, Lead Technical Consulting Engineer, and Md Khaledur Rahman, Graduate Technical Intern, Intel Corporation
  • Vectorization and SIMD Optimizations by Mayank Tiwari, Technical Consulting Engineer, and Rama Malladi, Graphics Performance Modeling Engineer, Intel Corporation
  • Boosting Performance of HPC Cluster Workloads Using Intel® MPI Library Tuning by Amarpal S Kapoor, Technical Consulting Engineer, and Marat Shamshetdinov, Software Development Engineer, Intel Corporation
  • Simplifying Cluster Use by Jeremy Siadal, Senior Software Engineer, Intel Corporation

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804