Parallel Universe Magazine - Issue 8, September 2011

Submitted: September 01, 2011 Last updated: September 01, 2011
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Detailed Description

Contents:

  • Letter from the Editor: Parallelism Programming: Who Signed Me Up for Writing a Book?, by James Reinders
    Reinders, chief evangelist and director of Intel® Software Development Products, shares how his opinions on Intel® Parallel Advisor have evolved, and explains why Flow Graph is his most favorite new feature of Intel® Threading Building Blocks.
     
  • HPC Study: Biophysicists and Mathematicians Embrace Parallelism with Intel® Parallel Advisor, by Zakhar A. Matveev
    Learn how a group of research scientists in Russia parallelized their applications in response to the growing data from biological experiences and increasing complexity of simulation requirements.
     
  • The Intel® Threading Building Blocks Flow Graph, by Michael J. Voss, Ph.D.
    User feedback inspired the Flow Graph feature in Intel® Threading Building Blocks, which allows programmers to express static and dynamic dependency graphs, as well as reactive or event-based graphs.
     
  • Intel® Parallel Studio XE SP1, by Michael D’Mello
    Intel® Parallel Studio XE combines Intel’s industry-leading C/C++ and Fortran compilers, high performance parallel libraries, error checking, code robustness, and performance profiling technologies into a single suite offering. The SP1 release now adds functionality to simplify the transition from multicore to many-core hardware platforms.
     

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

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