Flow Graph Analyzer

Visualize Parallelism Graphically represent and analyze your application’s critical path performance. Starting with a blank canvas, construct a flow graph application by interactively adding nodes and edges through a graphical interface.

Model Graphs in a Heterogeneous World

Flow Graph Analyzer (FGA) is a rapid visual prototyping environment. Any developer with Intel® Threading Building Blocks (Intel® TBB) flow graph applications or applications that can be expressed as flow graphs can benefit from this tool.

It assists developers with analyzing and designing parallel applications that use the Intel TBB flow graph interface.

  • Speed up algorithm design and express parallelism efficiently
  • Plan, validate, and model application design and performance before generating Intel TBB code
  • Create parallel applications that take advantage of multicore and heterogeneous systems
  • Pinpoint your performance tuning efforts by using the critical path analysis to reduce the set of nodes (even large graphs) to focus on

User Guide

Design Workflow

Create Intel TBB flow graph diagrams and generate C++ stubs as a starting point for further development. Employ a drag-and-drop paradigm for interactively constructing Intel TBB graphs.

Modeling Workflow

The technical preview feature is available in limited capacity and only supports dependency graphs. Use this workflow between the design and analysis steps to project the scalability of a dependency graph and iteratively refine the graph topology to maximize scalable performance.

Analyzer Workflow

Collect and visualize execution traces from Intel TBB flow graph applications. From FGA, you can explore the topology of your graphs, interact with a timeline of node executions, and project important statistics onto graph nodes.

Learn About Additional Features

Roofline Analysis

Optimize your application for memory and compute.

Vectorization Optimization

Enable more vector parallelism and improve its efficiency.

Thread Prototyping

Model, tune, and test multiple threading designs.

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804