Optimize vectorization: Quickly find high-impact opportunities to speed up your application safely.
Vectorize for Better Performance
Vectorization is the operation of Single Instruction Multiple Data (SIMD) instructions (like Intel® Advanced Vector Extensions and Intel® Advanced Vector Extensions 512) on multiple data objects in parallel within a single CPU core. This can greatly increase performance by reducing loop overhead and making better use of the multiple math units in each core.
A survey summary for all loops. Click the light bulb for recommendations. Double-click a loop to see the source with compiler messages.
The Survey report provides useful tips.
Trip Counts & FLOPS Analysis
Complementing the Survey report, these features help you make better-informed decisions about your vectorization strategy for particular loops and optimize already-parallel loops.
After identifying loops that can benefit most from optimization, save time by selecting only the loops on which you want to run more detailed reports, such as dependencies or a memory access patterns analysis.
Compilers may make conservative decisions during automatic vectorization to prevent errors from potential data dependencies. Use this report to identify whether dependencies actually exist for each of the selected loops, then conclusively discern whether it’s safe to force the compiler to vectorize them. If real dependencies are detected, the report provides additional details to help resolve them.
Memory Access Patterns (MAP) Report
Check for memory issues—such as noncontiguous memory accesses and unit stride versus nonunit stride accesses—which can lead to a significant slowdown of executing vector code.
"I’m a structural engineering researcher who designs and writes code (WARP3D), not a professional software developer. I never had the tools where it was relatively painless to optimize vectorization for measured runtime performance. I found Intel Advisor easy to use and very effective. When optimizing code, it is always a trade-off of effort versus reward. With Intel Advisor, a modest, focused effort on known hotspots yielded significant benefits."
— Robert H. Dodds, Jr., PhD; National Academy of Engineering (NAE); research professor, Department of Civil and Environmental Engineering, University of Tennessee (Knoxville)
"The Vectorization Advisor in Intel Advisor permitted me to focus my work where it really mattered. When you have only a limited amount of time to spend on optimization, it is invaluable."
— Gilles Civario, senior software architect, Irish Centre for High-End Computing
"The Vectorization Advisor in Intel Advisor fills a gap in code performance analysis. It can guide the informed user to better exploit the vector capabilities of modern processors and coprocessors."
— Dr. Luigi Iapichino, scientific computing expert, Leibniz Supercomputing Centre
"The use of Intel Advanced Vector Extensions 512 for Intel® Xeon® processors gave us the maximum code performance [when compared to] other architectures available on the market. Intel Advisor made it easier to find the cause of the bottlenecks and decide on the next optimization steps. It provided data to help us forecast the performance gain before we invested significant effort in implementation."
— Igor Kulikov, assistant professor, Novosibirsk State University
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804