Intel MKL also contains a number of BLAS-like extensions1:

  • Triangular GEMM routines: Compute a matrix-matrix product but update only the upper or lower triangular part of the result matrix
  • Batched GEMM routines: Perform multiple GEMM operations in parallel
  • Packed GEMM routines: Amortize internal packing costs across multiple GEMM operations

Sparse BLAS (Levels 1, 2, 3) & Solvers

In addition to the standard Sparse BLAS APIs, Intel MKL also supports unique two-stage inspector-executor Sparse BLAS APIs for higher performance. For clusters, use the included implementation of the PARDISO* sparse solver, iterative sparse solver, or a distributed version of the solver. Tackle large-scale sparse eigenvalue problems with the highly robust and scalable Extended Eigensolver (based on the FEAST eigenvalue solver).

See Performance Benchmarks

 

See below for further notes and disclaimers.1

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Product and Performance Information

1

Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more information, see Performance Benchmark Test Disclosure.

 

2

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804