Data Parallel C++(Beta)

A Standards-Based, Cross-Architecture Language

Intel® oneAPI DPC++ Compiler

  • Targets CPUs and accelerators through single-source code while permitting custom tuning
  • Builds on the Intel history of compiler performance leadership
  • Is built to the latest standards, including C++17 and SYCL*, to ensure portability and support of features like generic lambda expressions and variable templates
  • Interoperates with oneAPI performance, productivity, and threading libraries. For example, the Intel oneAPI DPC++ Library extends the C++ Standard Library to better support data parallelism productivity. 1

Learn More about the Intel® oneAPI DPC++ Library

FPGA Emulation and Compilation

For experienced FPGA developers, the Intel® oneAPI Data Parallel C++ Compiler enables you to target your acceleration workload to field-programmable platforms. Simply select the optional Intel® FPGA Add-On for oneAPI Base Toolkit, available when you download the Intel® oneAPI Base Toolkit.

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CUDA* Source Code Migration

The Intel DPC++ Compatibility Tool is a migration engine that transforms CUDA applications into a standards-based DPC++ code.

  • One-time-only migration ports both kernels and API calls.
  • Inline comments guide developers to produce output that can be most easily compiled with the Intel oneAPI DPC++ Compiler.
  • The process is further streamlined by command-line tools and IDE plug-ins.

Product and Performance Information

1Intel oneAPI DPC++ Compiler Stack supports multiple target devices through the DPC++ runtime and LLVM backend.

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804