Intel® oneAPI DPC++ Compiler(Beta)
A Standards-Based, Cross-Architecture Compiler
What It Is
- A high-performance compiler for the Data Parallel C++ (DPC++) language
- It allows developers to reuse code across hardware targets, including CPUs, GPUs, and FPGAs
How It Works
- It compiles C++, SYCL, and DPC++ source code
- It generates optimized binary host code and accelerator code
What You Need
- The Intel oneAPI DPC++ Compiler is part of the Intel® oneAPI Base Toolkit
- It interoperates with the toolkit’s oneAPI performance and threading libraries, and profiling and debugger tools
Explore the Intel® oneAPI Base Toolkit
Cross-Architecture Compiling
- Targets CPUs and accelerators through single-source code while permitting custom tuning
- Is built to the latest standards, including C++17 and SYCL*, to ensure portability and support of features like generic lambda expressions and variable templates
- Leverages well-proven LLVM compiler technology as well as Intel’s history of compiler leadership
FPGA Emulation and Compilation
- Enables experienced FPGA developers to target accelerations workloads to field-programmable platforms
- Is an optional add-on to the Intel oneAPI Base Toolkit
Access oneAPI Software
- Toolkits: Intel® oneAPI Base Toolkit and add-on toolkits for HPC, AI, IoT, and more
- Tools & Libraries: Intel® oneAPI DPC++ Compiler, Intel® oneAPI Math Kernel Library, Intel® Distribution for Python*, Intel® VTune™ Profiler, Intel® Advisor, and more
Use the Latest Intel Hardware
- Intel® Xeon® Scalable processors
- Intel® Xeon® processors with Intel® Graphics Technology
- Intel® FPGAs
Get the Intel® oneAPI Data Parallel C++ Compiler as Part of the Intel® oneAPI Base Toolkit
This foundational set of tools and libraries includes:
- Familiar tools and languages
- Advanced analysis and debugging tools
- Intel® DPC++ Compatibility Tool for CUDA code migration
Documentation & Code Samples
Documentation
Code Samples
Learn how to access oneAPI code samples in a tool command line or IDE.
FPGA Samples
- Tutorials on FPGA DPC++ Compile Flow
- Tutorials on FPGA-Specific DPC++ Extentions
- Tutorials Illustrating FPGA Design Best Practices
- QR Decomposition of Matrices
- Introduction to DPC++ Compilation for FPGA
- Incorporating Cross-language Libraries in DPC++ FPGA Kernels
- Cox Ross Rubinstein Option-Pricing Model
Key Specifications
Processors:
- Intel® Core™ processors Gen6 and newer
- Intel® Xeon® processors
GPUs:
- Intel® Processor Graphics Gen9
FPGAs:
- Intel® Programmable Acceleration Card with Intel®Arria® 10 GX FPGA
Host and target operating systems:
- Windows*
- Linux*
Languages:
- Data Parallel C++ (DPC++)
- C++
Development environments:
- Microsoft Visual Studio*
- Eclipse* IDE
Threading:
- Intel® oneAPI Threading Building Blocks
- Native threads
For more information, see the system requirements.
Ready to Get Started?
Product and Performance Information
1
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804