CPUs, GPUs, FPGAs: Managing the Alphabet Soup with Intel® Threading Building Blocks


Today’s hardware landscape is increasingly heterogeneous—a collection of specialized CPUs, GPUs and FPGAs that can make or break power and performance efficiency. Intel® Threading Building Blocks (Intel® TBB) helps address this challenge because the library acts as a coordination layer between the hardware (CPU, GPU, FPGA) and software environments.

When you attend this webinar, you’ll get help answering 3 key questions:

  1. How do you get your computation onto a device that is not necessarily programmed in C++?
  2. How do you figure out the execution order of your application, and how do you get notification of when a job is done in one device in order to get started with the other device?
  3. How do you optimize the various code pieces so tasks gets assigned to various kernels in a way to get optimal performance?





Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804