Exploiting Multi-Level Parallels in HPC Applications

Overview

Upon completion of this webinar, you will be familiar with advanced threading methods for the Intel® Xeon Phi™ coprocessor such as various approaches to nested parallelism within the part. It also discusses advanced optimizations for MPI/OpenMP* programs that use both coprocessors and the Intel® Xeon® processor in the host nodes.

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804