In this webinar, James Reinders, will cover the essential knowledge needed for effectively utilizing the extraordinary parallelism in the new Intel® Xeon Phi™ processor (code named Knights Landing) including best practices for code vectorization and parallelization, and some tips and tricks. James will highlight the Developer Access Program or DAP (http://dap.xeonphi.com/). He will cover the benefits of this turnkey solution for developers including exciting capabilities of Intel Parallel Studio XE 2016 (included in the DAP). Examples and advices are drawn from the new book Intel® Xeon Phi™ Processor High Performance Programming, Knights Landing Edition, (http://lotsofcores.com/KNLbook) by Jim Jeffers, James Reinders, and Avinash Sodani. James will touch on some exciting new features in Intel Parallel Studio XE 2017 beta (http://bit.ly/PSXE2017-Beta) that specifically assist development on Knights Landing and invite everyone to sign up for the betaicient profiling techniques can help dramatically improving the performance of your Python* code by detecting time, CPU, and memory bottlenecks. This session discusses the need, advantages, and common tools and techniques for profiling Python applications, followed by a demo of Intel® VTune Amplifier and its capabilities to profile both pure Python code and code heavily relying on C extensions.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804