Respect Programming Models – Manage Intel® Xeon Phi™ in your Clusters for Enhanced User Experience


High performance computing (HPC) cluster programming model number 1 has been MPI for the past 10 or more years. The advent of coprocessors and accelerators forced many users to rethink their strategies and re-structure the code, even though a clever setup of Intel® Xeon Phi™ systems allows using them without being forced to do so. This webinar will present a number of techniques to help system administrators with their tasks.

  • Overview of Intel Xeon Phi programming techniques
  • Basic requirements to get Intel Xeon Phi running
  • How to mount cluster file systems on the Intel Xeon Phi
  • User integration
  • Use of startup scripts and their role in batch scheduling
  • Live demo




Product and Performance Information


Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804