Memory Traffic Optimization

Overview

In Episode 9 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel® architectures” we discuss memory traffic optimization.

We discuss the requirement of data access locality in space and time and demonstrate techniques for achieving it:

  • Loop tiling
  • Cache-oblivious recursion
  • Loop fusion
  • Parallel first touch

We also review a sample application performing matrix-vector multiplication, and see how it’s optimized using these techniques.

In the hands-on part of the episode, we demonstrate the application of the discussed methods to the matrix-vector multiplication code.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804