Parallel Program Model on Intel® Xeon® and Intel® Xeon Phi™ Coprocessor

Overview

Upon completion of this webinar, you will be familiar with parallel programming models and their optimized use on clusters of Intel® Xeon® and Intel® Xeon Phi™ coprocessor. This webinar dives deeply into the coprocessor architecture including the software stack, the threading models, and the cache and memory architecture. It highlights the similarities and differences between the Intel Xeon Phi coprocessor and Intel Xeon processor “big cores” and discusses the various parallel programming models and optimization strategies.

Product and Performance Information

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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804