Part 1: Introduction to Intel® Xeon and Xeon Phi™ Architectures

Overview

In episode 1 of the “Hands-On Workshop (HOW) series on parallel programming and optimization with Intel® architectures”, we introduce Intel® Xeon® processors and Intel® Xeon Phi™ coprocessors and discuss their features and purpose.

We also begin our introduction to portable, future-proof parallel programming and discuss the pre-requisites for high performance on the Intel® Many Integrated Core Architecture (Intel® MIC Architecture):

• Thread parallelism
• Vectorization
• The optimized memory access pattern

The episode introduces the native model for programming Intel Xeon Phi coprocessors that allows us to re-use application code designed for general-purpose CPUs.

The hands-on part of the episode demonstrates how the Linux* operating system (OS) on the host inter-operates with the OS on coprocessors, and how to use Intel compilers to run native applications on coprocessors.

Product and Performance Information

1

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

Notice revision #20110804