High performance computing (HPC) codes have used MPI and similar models to scale to multiple nodes, but increasingly parallelism is also required within a node, and even within a single core. Application programmers must be prepared to address parallelism at the message passing, threading, and SIMD layers. Upon completion of this webinar you will become familiar with modern Intel parallel architectures and Intel® Xeon Phi™ architecture for both hardware and software.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserverd for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804