Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 18.0
The Intel® Manycore Platform Software Stack (Intel® MPSS) may be installed before or after installing the Intel® C++ Compiler.
Using the latest version of Intel® MPSS available is recommended. It is available from the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com as part of your Intel® Parallel Studio XE for Windows* registration.
Refer to the Intel® MPSS documentation for the necessary steps to install the user space and kernel drivers.
Intel® Parallel Studio XE 2018: Getting started with the Intel® C++ Compiler 18.0 for Windows* at <install-dir>\documentation_2018\en\compiler_c\ps2018\get_started_wc.htm. contains information on how to use the Intel® C++ Compiler from the command line and from Microsoft Visual Studio*.
Product documentation is linked from <install-dir>\documentation_2018\en\compiler_c\ps2018\get_started_wc.htm.
Online Help format in Microsoft Visual Studio*
New help menu items to link to online getting started documents.
Context sensitive help on F1 is not available
Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.
Japanese language support is not provided with this release of the product.
Product samples are now available online at Intel® Software Product Samples and Tutorials
If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.
For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.
The following features are new or significantly enhanced in this version. For more information on these features, please refer to the documentation.
If OS/HW work incorrectly and libirc gets a cache size of 0 from CPUID, it may cause performance degradation. In such case user can define env. variable __INTEL_LIBIRC_DEBUG=1 to identify the root cause and get the information about OS/HW issue, e.g. export __INTEL_LIBIRC_DEBUG=1
On clicking F1, It is possible to restore context sensitive help in Visual Studio of download and install documentation to the system. The link to the download instructions and packages is here.
Support for the following new cpuid(codenames)
In the following function attributes (meaning manual targeting of those functions to the specified cpu codename):
C/C++ __attribute__((cpu_dispatch( )))
C/C++ __attribute__((cpu_specific( )))
Integration support for Intel® C++ compiler added for Microsoft Visual Studio 2017*. We do support the integration for Microsoft* Visual Studio 2017 version released before the Intel® Compiler update or initial version release date, e.g. 18.0 Update 3 supports integration for Microsoft* Visual Studio 2017 15.6 and older.
Refer to System Requirements for additional information.
New keywords for existing
#pragma omp ordered simd
#pragma omp ordered simd monotonic()
#pragma omp ordered simd overlap(expr)
#pragma omp simd reduction(=: list)
Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details
You can tune the zmm code generation done by the compiler with the new additional option -qopt-zmm-usage:low|high. The argument value of low provides a smooth transition experience from - Intel® Advanced Vector Extensions 2 (Intel® AVX2) ISA to Intel® Advanced Vector Extensions 512 (Intel® AVX-512) ISA on a Intel® Xeon® Platinum processor (formerly code name Skylake), such as for enterprise applications. Tuning for ZMM instruction use via explicit vector syntax such as #pragma omp simd simdlen() is recommended. The argument value of high is recommended for applications, such as HPC codes, that are bounded by vector computation to achieve more compute per instruction through use of the wider vector operations. The default value is low for Skylake server microarchitecture-family compilation targets and high for Intel® Core™ /Intel® Many Integrated Core Architecture (Intel® MIC Architecture) Intel® AVX-512 combined compilation targets.
Profile Guided Optimization (PGO) Hardware-based event sampling is a new low overhead model to get (many) benefits of PGO using the Intel® Compiler and the Intel® VTune™ Amplifier. Data collection works on systems where Intel® VTune™ Amplifier is supported.
Please refer the Intel® C++ Compiler 18.0 User and Reference guide for more details
Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.
Intel defined 256-bit vector intrinsics
_m256_extract_epi8/epi16(__m256i a, const int index) return int instead of __int8/__int16 values.
New option forces use of SVML where currently LIBM is used, for scalar math. This guarantees bitwise-same result of computations made with vectorized code vs computations made with scalar code. With this feature the compiler vectorizes math functions in /fp:precise FP model and vectorized code produces results consistent with scalar code results.
Control-flow Enforcement Technology (CET) defends a program from certain attacks that exploit vulnerabilities, e.g. Return-oriented Programming (ROP) and similarly Call/Jmp-oriented Programming (COP/JOP). Please refer to the preview document for more details.
New compiler option /Qcf-potection[:keyword] introduced in the compiler to support CET.
The compiler default behaviour is changed for SVML functions and a call to cpu-specific SVML entry is performed. Specifying new option /Qimf-force-dynamic-target reverts to the previous behavior and dynamic SVML dispatching is used.
Language features for task reductions from the OpenMP* Technical Report 4 : Version 5.0 Preview 1 specifications are now supported.
For more information, see the compiler documentation or the link to the OpenMP* Specification above.
#pragma omp taskloop[clause[[,]clause]..]
#pragma omp for schedule :
NONMONOTONICmodifiers extenstion to schedule clause to enhance user control of how interations of the for loop are divided among threads of team. See the Intel® C++ Compiler User’s Guide for more details.
reduction(reduction-identifier:list)If a list item is an array section, it is treated as if reduction clause is applied to each seperate element of the section. The elements of the private array sections will be allocated contiguously
The Intel® C++ Compiler 18.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:
The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:
For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.
All the –o* options deprecated in the previous release have been replaced with –qo* options in this release with one noted exception, there is no change to the –o option for Linux* and macOS* used to name the output file.
On Windows*, this change impacts compiler options passed to the target compilation with the /Qoffload-option Compiler option.
A new diagnostic is issued when any now replaced –o option is used. For example:
$ icc -openmp example.c
icc: command line error: option '-openmp' is not supported. Please use the replacement option '-qopenmp'
For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler 18.0 User's Guide.
Intel® Cilk™ Plus is a deprecated feature in the Intel® C++ Compiler 18.0. Prefer to use OpenMP-based syntax for offloading to the processor graphics. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus
icl: remark #10421: The IA-32 target wrapper binary 'icl' is deprecated. Please use the compiler startup scripts or the proper Intel(R) 64 compiler binary with the '-Qm32' option to target the intended architecture
Support for installation on IA-32 hosts has been removed. Support for generating code for 32-bit targets is supported on 64-bit hosts (only) via compiler option /Qm32
_GFX_enqueue has been removed and should be replaced with _GFX_offload
Due to a limitation with the Intel® Manycore Platform Software Stack (Intel® MPSS) supporting the Intel® Xeon Phi™ coprocessor x200 product family, Microsoft Visual Studio 2013* is not currently usable for execution of offload applications. While you can build offload applications with Microsoft Visual Studio 2013*, the execution fails with the error: "The remote process indicated that the following libraries could not be loaded libioffload_target.so.5 libiomp5.so libcilkrts.so.5 offload error: cannot start process on the device 0 (error code 19)" Running the offload application built under Microsoft Visual Studio 2013* requires using either Microsoft Visual Studio 2015* or 2017 run as ‘devenv’ from a "Compiler 18.0 Beta for Intel 64 Visual Studio 2015/2017” command-prompt window. However, This error message is only for vs2015/2017 run from shortcut, not from cmd with PSXE environment. VS2013 fails with another issue and messages.The recommended work around is to use either Microsoft Visual Studio 2015* or 2017 exclusively for building and running Offload applications targeting the Intel® Xeon Phi™ coprocessor. This limitation may be addressed in a future the Intel® Manycore Platform Software Stack (Intel® MPSS).
When using the /Qcheck-pointers option, the runtime library libchkp.dll must be linked in. When using options like /MD with /Qcheck-pointers, be aware that this dynamic library will be linked in regardless of your settings. See the article at http://intel.ly/1jV0eWD for more information.
There is a limitation of Visual Studio* internal browser that some multi-pane documents do not display correctly, the table of contents appears in the left pane, but the right pane does not display any content.
Workaround: Access the same documentation from the Visual Studio Help menu.
A general protection fault caused by an unaligned data access may occur when an application is built using two different compilers - the Microsoft Visual C++ 2013* compiler and the Intel® C++ Compiler 15.0 or above. The problem may arise when 256 vector bit type parameters are passed by reference in a call, when the caller is built with Visual C++*, and the parameters are accessed by functions built with the Intel C++ Compiler.
The problem arises due to a mismatch in the alignment of the 256 vector bit type parameters.
This problem will not occur when the /Qx<code> compiler option is used with <code> equal to AVX or with a newer code value, such as CORE-AVX-I, CORE-AVX2, etc., due to the fact that unaligned access instructions are used in these instances unless __mm256_stream_* (non-temporal data load/store intrinsics) are used explicitly in the application source code.
There are different integration issues observed with Microsoft* Visual Studio 2017. Problems are intermittent and not reproducible on every system. We haven't seen integration issues with latest Visual Studio 2017 version 15.3.3. Please refer to https://software.intel.com/en-us/articles/intel-software-development-tools-integration-to-vs2017-issue for details.
Starting from Visual Studio 2017 version 15.4 context menu item Intel Compiler > Guided Auto Parallelism > Run Analysis on Routine… is unavailable for the routine selected in the editor. You can still run analysis on range of lines, file or project. The issue is planned to be fixed in a future release.
There is an issue when viewing the Intel Compiler Documentation in Microsoft Edge* browser on Japanese Windows 10 OS. The upper left corner [Content][Index][Search] buttons does not work. When clicking on it, it results in blank screen.
This issue is being investigated. Please use Internet Explorer to view the Intel Compiler Documentation. To set the default browser to Internet Explorer, google search "how to make Internet Explorer default browser on Windows 10".
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
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Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. Go to:
The Intel® C++ Compiler is provided under Intel's End User License Agreement (EULA).
Please consult the licenses included in the distribution for details.
Intel, Intel logo, Pentium, Core, Atom, Iris, Intel® Xeon®, Intel® Xeon Phi™, and Cilk are trademarks of Intel Corporation in the U.S. and other countries.
* Other names and brands may be claimed as the property of others.
Copyright © 2019 Intel Corporation. All Rights Reserved.
Los compiladores Intel pueden o no optimizar al mismo nivel para los microprocesadores que no son Intel en optimizaciones que no son exclusivas de los microprocesadores Intel. Estas optimizaciones incluyen los conjuntos de instrucciones SSE2, SSE3 y SSSE3, y otras optimizaciones. Intel no garantiza la disponibilidad, funcionalidad o eficacia de ninguna optimización en microprocesadores que no sean fabricados por Intel. Las optimizaciones dependientes del microprocesador en este producto fueron diseñadas para usarse con microprocesadores Intel. Ciertas optimizaciones no específicas de la microarquitectura Intel se reservan para los microprocesadores Intel. Consulte las guías de referencia y para el usuario para obtener más información acerca de los conjuntos de instrucciones específicos cubiertos por este aviso.
Revisión del aviso n.° 20110804