Please see the licenses included in the distribution as well as the Disclaimer and Legal Information section of these release notes for details. Please see the following links for information on this release of the Intel® C++ Compiler 19.0
This section highlights important from the previous product version and changes in product updates.
This is release for Intel® Compilers 2019 Update 8, compilers version 19.0.8. Highlights for this release:
Note: Advanced optimization options or very large programs may require additional resources such as memory or disk space.
Parallel Studio XE 2019 : Getting Started with the Intel® C++ Compiler 19.0 for mac OS* at <install_dir>/documentation_2019/en/compiler_c/ps2019/get_started_mc.htm contains information on how to use the Intel® C++ Compiler from the command line and from Xcode*.
Product documentation is linked from <install-dir>/documentation_2019/en/compiler_c/ps2019/get_started_mc.htm. Full documentation for all tool components is available at the Intel® Parallel Studio XE Support page.
Offline core documentation is removed from the Intel® Parallel Studio XE installed image. The core documentation for the components of Intel® Parallel Studio XE are available at the Intel® Software Documentation Library for viewing online. You can also download an offline version of the documentation from the Intel® Software Development Products Registration Center: Product List > Intel® Parallel Studio XE Documentation.
Product samples are now available online at Intel® Software Product Samples and Tutorials
Refer to the Redistributable Libraries for Intel® Parallel Studio XE for more information.
If you did not register your compiler during installation, please do so at the Intel® Software Development Products Registration Center at http://registrationcenter.intel.com. Registration entitles you to free technical support, product updates and upgrades for the duration of the support term.
For information about how to find Technical Support, Product Updates, User Forums, FAQs, tips and tricks, and other support information, please visit: http://www.intel.com/software/products/support/
Note: If your distributor provides technical support for this product, please contact them for support rather than Intel.
This option is supported in versions 19.0 update 8 of the compiler and above. The details about this option can be found in the Intel® C++ Compiler 19.1 Developer Guide and Reference here.
To find more information, see https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
The Intel® Software License Manager has been updated to version 2.9 for this release. You must upgrade to this version before installing Intel Parallel Studio XE 2019 Update 4 with a floating license. Please refer for more details:
Please refer here for more details.
Currently "#pragma omp simd" overrides FP value and exception safe settings. The following options change that legacy behaviour and produce value and exception safe code even for SIMD loops.
OpenMP SIMD specification and FP model flag can contradict in the requirement. Compiler’s default is to follow OpenMP specification and vectorize the loop. With this new flag, programmer can override so that the compiler follows the FP model flag instead and serialize the loop
Note1: When –qsimd-honor-fp-model is used and OpenMP SIMD reduction specification is the only thing causing serialization of entire loop addition of qsimd-serialize-fp-reduction will result in vectorization of the entire loop except reduction calculation which will be serialized.
Note2: This option does not affect auto-vectorization of loops.
code names supported :cascadelake, kabylake, coffeelake, amberlake, whiskeylake.
#pragma vector dynamic_align[(pointer)] #pragma vector nodynamic_align
With no pointer specified, compiler behaves normally (automatically decides which pointer has to be aligned or doesn’t generate peel loop at all). With pointer specified, compiler generates peel loop for that pointer. With nodynamic_align clause, the compiler will not generate a peel loop.
#pragma vector vectorlength(vl1,vl2, .. , vln)
Vectorizer chooses best vector length from the list according to cost model. If all vector length from the list are not profitable, the loop remains scalar. This pragma doesn’t force vectorization, thus it can be safely used for all loops.
Language features from the OpenMP* Technical Report 6 : Version 5.0 Preview 2 specifications are now supported.
#pragma omp simd[parallel] scan(scan-op: item-list)
#pragma omp inclusive_scan(item-list)
#pragma omp simd[parallel] scan(scan-op: item-list)
#pragma omp inclusive_scan(item-list)
For more information, see the compiler documentation or the link to the OpenMP* Specification above.
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++17 (Windows*) or -std=c++17 (Linux*/macOS*) options:
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++14 (Windows*) or -std=c++14 (Linux*/macOS*) options:
The Intel® C++ Compiler 19.0 supports the following features under the /Qstd=c++11 (Windows*) or -std=c++11 (Linux*/macOS*) options:
The Intel® C++ Compiler supports the C11 features under the /Qstd=c11 (Windows*) or -std=c11 (Linux*/macOS*) options:
For details on these and all compiler options, see the Compiler Options section of the Intel® C++ Compiler 19.0 User's Guide.
For a list of deprecated compiler options, see the Compiler Options section of the Intel® C++ Compiler19.0 User's Guide.
Intel(R) C++ Compiler is installed with Parallel STL, an implementation of the C++ standard library algorithms with support for execution policies.
To learn more, please refer to article https://software.intel.com/en-us/get-started-with-pstl
Intel® Cilk™ Plus is a deprecated feature since Intel® C++ Compiler 18.0. For more information see Migrate Your Application to use OpenMP* or Intel® Threading Building Blocks (Intel® TBB) Instead of Intel® Cilk™ Plus
Removed support for 32 bit applications on macOS
Starting with the 19.0 release of the Intel® C++ Compiler, macOS 32-bit applications are no longer supported. If you want to compile 32-bit applications, you should use an earlier version of the compiler and Xcode* 9.4 or earlier.
Tachyon deprecated from samples
In macOS 10.15, apple removed openGL framework, hence PSXE samples such as Tachyon uses openGL is also deprecated.
Xcode* 10 and Xcode* 11, new build system not supported
The Xcode 10 Beta introduced a “New Build System (Default)” which currently do not support custom compilers.You will see the error "no rule to process file" when building an Intel C++ Compiler project within XCode 10 and Xcode 11. To use Intel compilers, switch to “Legacy Build System” in Project Settings.
Slow License Checkout macOS* 10.15 Catalina*
The license checkout performance on macOS Catalina 10.15 is roughly 1.1 seconds per source file. This is a 10x slowdown on this OS compared to previous versions of macOS. We are evaluating our license technology for a solution but at this time we have not root caused the issue. If this slowdown is an issue, please revert back to the previous macOS 10.14 where this slowdown does not occur.
unseq and par_unseq policies only have effect with compilers that support '#pragma omp simd' or '#pragma simd. Parallel and vector execution is only supported for a subset of algorithms if random access iterators are provided, while for the rest execution will remain serial. Depending on a compiler, zip_iterator may not work with unseq and par_unseq policies.
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.
Notice revision #20110804
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Please consult the licenses included in the distribution for details.
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Los compiladores Intel pueden o no optimizar al mismo nivel para los microprocesadores que no son Intel en optimizaciones que no son exclusivas de los microprocesadores Intel. Estas optimizaciones incluyen los conjuntos de instrucciones SSE2, SSE3 y SSSE3, y otras optimizaciones. Intel no garantiza la disponibilidad, funcionalidad o eficacia de ninguna optimización en microprocesadores que no sean fabricados por Intel. Las optimizaciones dependientes del microprocesador en este producto fueron diseñadas para usarse con microprocesadores Intel. Ciertas optimizaciones no específicas de la microarquitectura Intel se reservan para los microprocesadores Intel. Consulte las guías de referencia y para el usuario para obtener más información acerca de los conjuntos de instrucciones específicos cubiertos por este aviso.
Revisión del aviso n.° 20110804