Flow Graph Analyzer

Visualize Parallelism Graphically represent and analyze your application’s critical path performance. Starting with a blank canvas, construct a flow graph application by interactively adding nodes and edges through a graphical interface.

Model Graphs in a Heterogeneous World

Flow Graph Analyzer (FGA) is a rapid visual prototyping environment. Any developer with Intel® Threading Building Blocks (Intel® TBB) flow graph applications or applications that can be expressed as flow graphs can benefit from this tool.

It assists developers with analyzing and designing parallel applications that use the Intel TBB flow graph interface.

  • Speed up algorithm design and express parallelism efficiently
  • Plan, validate, and model application design and performance before generating Intel TBB code
  • Create parallel applications that take advantage of multicore and heterogeneous systems
  • Pinpoint your performance tuning efforts by using the critical path analysis to reduce the set of nodes (even large graphs) to focus on

User Guide

Design Workflow

Create Intel TBB flow graph diagrams and generate C++ stubs as a starting point for further development. Employ a drag-and-drop paradigm for interactively constructing Intel TBB graphs.

Modeling Workflow

The technical preview feature is available in limited capacity and only supports dependency graphs. Use this workflow between the design and analysis steps to project the scalability of a dependency graph and iteratively refine the graph topology to maximize scalable performance.

Analyzer Workflow

Collect and visualize execution traces from Intel TBB flow graph applications. From FGA, you can explore the topology of your graphs, interact with a timeline of node executions, and project important statistics onto graph nodes.

Learn About Additional Features

Roofline Analysis

Optimize your application for memory and compute.

Vectorization Optimization

Enable more vector parallelism and improve its efficiency.

Thread Prototyping

Model, tune, and test multiple threading designs.

Información sobre productos y desempeño

1

Los compiladores Intel pueden o no optimizar al mismo nivel para los microprocesadores que no son Intel en optimizaciones que no son exclusivas de los microprocesadores Intel. Estas optimizaciones incluyen los conjuntos de instrucciones SSE2, SSE3 y SSSE3, y otras optimizaciones. Intel no garantiza la disponibilidad, funcionalidad o eficacia de ninguna optimización en microprocesadores que no sean fabricados por Intel. Las optimizaciones dependientes del microprocesador en este producto fueron diseñadas para usarse con microprocesadores Intel. Ciertas optimizaciones no específicas de la microarquitectura Intel se reservan para los microprocesadores Intel. Consulte las guías de referencia y para el usuario para obtener más información acerca de los conjuntos de instrucciones específicos cubiertos por este aviso.

Revisión del aviso n.° 20110804