Software Tools

The Intel® Quartus® Prime Software is a complete CAD system for designing digital circuits. The Intel Quartus Prime Lite Edition software is recommended for teaching as it does not require a license. The licensed commercial version of the Intel Quartus Prime and Prime Pro Edition software is available for installation in university laboratory facilities.

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To determine the appropriate version of the Intel Quartus Prime Software for the device on your board, use the Select by Device tab on the download page or check the Device Support List.

When targeting Intel® Stratix® 10 or Intel® Arria® 10 devices, you may use the Intel Quartus Prime Software, which is available for use on the Intel® DevCloud.

This is a widely used logic simulation tool for verification and debugging of digital circuits. Intel provides a version that includes libraries for Intel® FPGAs. You can download the ModelSim-Intel FPGA Edition Software program along with the Intel Quartus Prime Software.

This software is used for designing and implementing embedded computer systems. It facilitates the creation of embedded systems that include processors, memory interfaces, and a variety of I/O devices. The Platform Designer is included as a part of the Intel® Quartus® Prime Software.

The Monitor Program allows students to easily compile and debug both assembly language and C programs. It supports both the Arm* Cortex*-A9 and Nios® II processors. The Monitor Program includes standard debugging features, such as single-step, breakpoints, register and memory display, and so on.

This software is available as part of the Intel FPGA Academic Program Installer. The suite also contains the program intellectual property (IP) cores and computer systems examples.

The Installer contains the Monitor Program and computer systems examples. Depending on the selected version, the installer also contains the Intel® FPGA Academic Program IP cores or their patches (see the University Program IP Core section above for more details).

Provided SD card images contain an Ubuntu-based Linux* distribution for use with SoC-based DE-series boards. The Linux distribution can be used for embedded Linux exercises and projects. Features include:

  • Command line interface through serial UART or SSH
  • Desktop interface through VNC connection
  • Command line FPGA programming capability
  • Automatic FPGA programming at boot up using the default computer system for the board (the same system that is included with the Monitor Program)
  • Built-in GCC toolchain for compiling code natively on the board
  • Sample applications that demonstrate FPGA communication and driver development
  • OpenCL™ software support for our boards that have the OpenCL software board support package (BSP)

To get started: 

  1. Follow the instructions in the Use Linux on Terasic DE-Series Boards tutorial.
  2. Download the appropriate SD card image.

This SDK allows you to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL software C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, and push the longer compile time to the end once you are satisfied with your kernel code results. Leverage prewritten optimized OpenCL software or register transfer level (RTL) functions, calling them from the host or directly from within your OpenCL kernels.

Intel® HLS Compiler accelerates FPGA design by enabling hardware developers to work at higher levels of abstraction using untimed C/C++. Simulation times for abstract models developed in C/C++ typically finish in seconds compared to register transfer level (RTL) simulations that can take minutes or hours. Intel HLS Compiler generates production quality RTL that is device optimized for Intel® FPGAs.

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This tool enables system design for digital signal processing (DSP). It contains a library of modules that can be used in the industry-standard MathWorks* Simulink tools. The DSP Builder for Intel® FPGAs is available free of charge for universities.

The Monitor Program allows students to easily compile and debug both assembly language and C programs. It supports both the Arm* Cortex*-A9 and Nios® II processors. The Monitor Program includes standard debugging features, such as single-step, breakpoints, register and memory display, and so on.

This software is available as part of the Intel FPGA Academic Program Installer. The suite also contains the program intellectual property (IP) cores and computer systems examples.

The Installer contains the Monitor Program and computer systems examples. Depending on the selected version, the installer also contains the Intel® FPGA Academic Program IP cores or their patches (see the University Program IP Core section above for more details).

Provided SD card images contain an Ubuntu-based Linux* distribution for use with SoC-based DE-series boards. The Linux distribution can be used for embedded Linux exercises and projects. Features include:

  • Command line interface through serial UART or SSH
  • Desktop interface through VNC connection
  • Command line FPGA programming capability
  • Automatic FPGA programming at boot up using the default computer system for the board (the same system that is included with the Monitor Program)
  • Built-in GCC toolchain for compiling code natively on the board
  • Sample applications that demonstrate FPGA communication and driver development
  • OpenCL™ software support for our boards that have the OpenCL software board support package (BSP)

To get started: 

  1. Follow the instructions in the Use Linux on Terasic DE-Series Boards tutorial.
  2. Download the appropriate SD card image.

This SDK allows you to abstract away the traditional hardware FPGA development flow for a much faster and higher level software development flow. Emulate your OpenCL software C accelerator code on an x86-based host in seconds, get a detailed optimization report with specific algorithm pipeline dependency information, and push the longer compile time to the end once you are satisfied with your kernel code results. Leverage prewritten optimized OpenCL software or register transfer level (RTL) functions, calling them from the host or directly from within your OpenCL kernels.

Intel® HLS Compiler accelerates FPGA design by enabling hardware developers to work at higher levels of abstraction using untimed C/C++. Simulation times for abstract models developed in C/C++ typically finish in seconds compared to register transfer level (RTL) simulations that can take minutes or hours. Intel HLS Compiler generates production quality RTL that is device optimized for Intel® FPGAs.

Learn More

This tool enables system design for digital signal processing (DSP). It contains a library of modules that can be used in the industry-standard MathWorks* Simulink tools. The DSP Builder for Intel® FPGAs is available free of charge for universities.

 

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