Parallel fault simulation algorithm for multi-core systems with common memory

Fault simulation for sequential circuits numbers among the highly compute-intensive tasks in the integrated circuit design process. In this paper we propose a new parallel fault simulation algorithm for multi-core workstations with common memory. We use dynamic fault grouping for each input test vector. Also each formed group is simulated in separate thread. Also we study the scalability of proposed algorithm. We report results for the ISCAS-89 benchmark circuits obtained on Intel’s MTL with 12 computational cores.

Unter der Lizenz Creative Commons License stehen Downloads zur Verfügung. Jetzt herunterladen
Nähere Informationen zur Compiler-Optimierung finden Sie in unserem Optimierungshinweis.