Intel® Developer Zone:
Intel ISA Extensions

Ankündigungen
 

Support for various extensions to the Intel Instruction Set Architecture, including but not limited to:

  • Intel® AVX, which provides the infrastructure and building blocks for delivering the performance required by the growing needs of applications such as financial analysis, media content creation, encoding and encryption, natural resource industry, and High Performance Computing (HPC)
  • Intel® MPX, which provides the infrastructure for software to trap buffer overflow errors before they can be exploited by malware
  • Intel® SHA Extensions, which provide improved performance for applications using the commonly employed Secure Hash Algorithm to obtain greater data integrity, message authentication, digital signatures and data de-duplication

 
Thema / Thema-Starter Beitragsdatum Antworten Letzter Beitragaufsteigend sortieren
Normales Thema Could intel somehow initiate migration/cleanup for x86 instruction set?
von htuh
Do, 12/11/2009 - 16:13 0
von htuh
Di, 12/01/2010 - 10:45
Normales Thema TSC Problem
von faball
Fr, 27/11/2009 - 02:52 0
von faball
Mo, 11/01/2010 - 09:36
Normales Thema mul instruction latency
von tthsqe
Sa, 09/01/2010 - 22:52 3
von Max Locktyukhin...
Sa, 09/01/2010 - 22:52
Normales Thema Debugging SSE/SSE2 ?
von gol
Do, 24/12/2009 - 03:26 10
von gol
Mi, 06/01/2010 - 04:54
Normales Thema question on avx instruction encoding
von tthsqe
Fr, 01/01/2010 - 02:19 9
von mariaosawa
Fr, 01/01/2010 - 02:19
Normales Thema ow to calculate latency and throughput of instruction?
von maa1
Do, 17/12/2009 - 10:32 2
von maa1
Do, 17/12/2009 - 10:32
Normales Thema We need standardization of the x86 instruction set
von Agner
Sa, 05/12/2009 - 09:35 10
von Igor Levicki
Sa, 05/12/2009 - 09:35
Normales Thema VEX prefix and ymm state saving support
von yuhong2
Do, 03/12/2009 - 23:19 1
von Brijender Bhart...
Fr, 04/12/2009 - 09:00
Normales Thema Illegal Instruction -- Intel SDE with AES instructions
von rksm
Di, 01/12/2009 - 07:58 3
von Mark Charney (Intel)
Di, 01/12/2009 - 07:58
Normales Thema How does address be mapped onto a memory bank
von zhangyihere
Di, 01/12/2009 - 02:04 0
von zhangyihere
Di, 01/12/2009 - 07:30
Normales Thema PTEST improvement?
von Matthias Kretz
Di, 24/11/2009 - 00:59 1
von Max Locktyukhin...
Di, 24/11/2009 - 00:59
Normales Thema Low rate on sse2 code
von maa1
Mo, 23/11/2009 - 11:39 0
von maa1
Mo, 23/11/2009 - 11:39
Normales Thema How many info could I get to estimate DRAM bandwidth?
von hchen229
Di, 17/11/2009 - 08:17 1
von Roman Dementiev...
Di, 17/11/2009 - 08:17
Normales Thema Understanding my Benchmarks
von Matthias Kretz
Di, 10/11/2009 - 08:13 5
von Matthias Kretz
Di, 10/11/2009 - 08:13
Normales Thema Why "subq" as allocate by ICC-v10.0 but not as prologue, but ICC-v11.0 uses "pushq" as prologue?
von srimks
Mi, 21/01/2009 - 01:10 3
von Sergey Maslov (...
Mo, 02/11/2009 - 22:18
Normales Thema sse4.2 instructions
von westmere
Fr, 01/05/2009 - 16:03 7
von Shih Kuo (Intel)
Mo, 02/11/2009 - 09:54
Normales Thema Opcode semantics
von matt.j
Do, 13/08/2009 - 18:24 3
von c0d1f1ed
Mo, 02/11/2009 - 00:38
Normales Thema help on detecting stalls(identifying structural hazards) in assembly code
von ddmetro
Mi, 28/10/2009 - 10:18 1
von Tim Prince
Mi, 28/10/2009 - 10:18
Normales Thema is there a standard format in which we provide architecture specific information to a software
von ddmetro
So, 25/10/2009 - 16:24 0
von ddmetro
So, 25/10/2009 - 16:24
Normales Thema how to turn off out-of-order execution in Intel processor
von ddmetro
So, 25/10/2009 - 14:32 3
von ddmetro
So, 25/10/2009 - 14:32
Neue Beiträge
Keine neuen Beiträge
Heißes Thema mit neuen Beiträgen
Heißes Thema ohne neue Beiträge
Markiertes Thems
Gesperrtes Thema
Nähere Informationen zur Compiler-Optimierung finden Sie in unserem Optimierungshinweis.