Are the MTRRs, PAT, and CR0 (CD & NW) registers the only means to controling the caching of memory? Is there any other way to disable the cache? I have verified that the MTRRs type is 06 (Writeback), the PAE of all pages point to the first PATindex which is set to 06(Writeback), andwhether I set or clear the CD and NW bits of the CR0, I still get thesame performance countvalues for aL3cache miss. Myassumption is that ifthe MTRR and PAT are writeback and Iset the CD&NW bits of CR0 then all levels of cacheare disabled. But if I clear the CD & NW bits of CR0 then all levels of cache are enabled. Is this incorrect?
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