STM implementation in STM compiler

STM implementation in STM compiler

I am curious, what STM implementation used in STM compiler? Can you give some links to description, or to academic papers, or to patents.
Whether it's lock-free or obstruction-free or lock-based? Whether eager or commit time locking is used? Whether timestamp based validation is used or not? Whether it's word based, or object based? And so on.

All about lock-free algorithms, multicore, scalability, parallel computing and related topics: http://www.1024cores.net
6 Beiträge / 0 neu
Letzter Beitrag
Nähere Informationen zur Compiler-Optimierung finden Sie in unserem Optimierungshinweis.

We have a paper accepted for OOPSLA08, which is also available here www.adamwelc.org/papers/oopsla08.pdf

I think it should answer most of your questions. (The answer toat least one ofyour "a or b" questions is "yes" )

Thank you. It seems that the paper is exactly what I want.

I'm also interesting, what is the destination of STM Compiler? Will STM be incorporated into mainline C++ compiler? Or is it testbed for Hardware TM?

All about lock-free algorithms, multicore, scalability, parallel computing and related topics: http://www.1024cores.net

randomizer:Thank you. It seems that the paper is exactly what I want.

I'm also interested, what is the destination of STM Compiler?

Will STM be incorporated into mainline C++ compiler?

Or is it testbed for Hardware TM?

Intel has noannouncedproduct plans for either hardware or software transactional memory products. Software in WhatIf is experimental, and being in WhatIf does not guarantee transition to a product, or continued support. (Basically you're insane if you base your own product on something in WhatIf ).

Our interest is to try to understand things like

  • what language features are required by transactional programs in C/C++
    • explicit abort
    • explicit retry
    • interoperation with
      • locks
      • I/O
      • standard runtime libraries (malloc, strings, ...)
      • dynamic libraries
      • nested parallelism
  • what semantics are acceptable
  • what overhead is acceptable
    • how many function annotations can you stand before you give up
    • how much code bloat,
    • how low a performance

My personal opinion (not that of Intel, or even all of the team working on the compiler and runtime) is that the jury is still out on the value of transactions in native compiled code.

MADjhcownie:

Intel has noannouncedproduct plans for either hardware or software transactional memory products. Software in WhatIf is experimental, and being in WhatIf does not guarantee transition to a product, or continued support. (Basically you're insane if you base your own product on something in WhatIf ).

Ok, I see. Thank you.
I was just thinking that maybe there are already some plans defined wrt STM.

All about lock-free algorithms, multicore, scalability, parallel computing and related topics: http://www.1024cores.net
MADjhcownie:

My personal opinion (not that of Intel, or even all of the team working on the compiler and runtime) is that the jury is still out on the value of transactions in native compiled code.

Do you mean the value of *software* transactional memory? Or the value of any TM, including also those backed up by *hardware* transactional memory?

All about lock-free algorithms, multicore, scalability, parallel computing and related topics: http://www.1024cores.net

Melden Sie sich an, um einen Kommentar zu hinterlassen.