Bus Data Ready (This Processor) event

Bus Data Ready (This Processor) event

The vtune reference guide describes Bus Data Ready (This Processor) event as follows:

This event counts the number of front-side bus clocks that the bus is transmitting data driven by the processor core, including full reads|writes and partial reads|writes and implicit writebacks.

My question is that:

1. Does this event count UC type of memory access?
2. Does this event count hardware and software prefetch?
3. I think this only counts the data access, not instruction memory access, right?

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